Flash memory has gained wide acceptance for its non-volatile storage, which is ideal for portable devices that may lose power, since the data is not lost when stored in the flash memory. Flash memories are constructed from electrically-erasable programmable read-only memory (EEPROM) cells.
Rather than use a randomly-addressable scheme such as is common with dynamic-random-access memory (DRAM), many flash memories use a block-based addressing where a command and an address are sent over the data bus and then a block of data is read or written. Since the data bus is also used to send commands and addresses, fewer pins are needed on the flash-memory chip, reducing cost. Thus flash memory is often used as a mass-storage device rather than a randomly-addressable device.
Universal-Serial-Bus (USB) has become a popular standard interface for connecting peripherals to a host such as a personal computer (PC). Peripheral Component Interconnect (PCI), Personal-Computer Memory Card International Association (PCMCIA) and PCI-Express are other bus and card standards. USB-based flash-memory storage devices or “drives” have been developed to transport data from one host to another, replacing floppy disks. While large external flash drives may be used, smaller USB flash drives known as key-chain or key drives have been a rapidly growing market.
A USB flash-memory device such as a key drive can be constructed from a microcontroller, a flash-memory controller or interface, and one or more flash-memory chips. A serial interface on the microcontroller connects to the USB bus to the host, and data from the serial interface is transferred through the microcontroller to the flash controller and then written to the flash-memory chips.
FIG. 1 shows a prior-art interface to a flash-memory chip. Flash-memory chip 12 has 8-bit I/O bus 14 that connects to controller 10. Controller 10 could be a microcontroller in a flash drive or a flash-memory card. Address, data, and commands are sent over 8-bit I/O bus 14 to flash-memory chip 12 using time-multiplexing. Eight bits of address, data, or command information can be transferred in parallel at a time over 8-bit I/O bus 14.
Several control signals on control bus 16 are used to coordinate transfer of address, data, and commands over 8-bit I/O bus 14. For example, an address-strobe signal can indicate when address signals can be latched into flash-memory chip 12, and a data strobe can indicate when data from flash-memory chip 12 can be latched by controller 10.
Although 8-bit I/O bus 14 is much more compact than if separate address and data buses were used, for some applications even the 8-bit bus is less than ideal. When the pins needed by 8-bit I/O bus 14 and flash-memory chip 12 are counted, as many as 16 signal pins are used for the interface to flash-memory chip 12. Several power and ground pins may be needed, so the total pin count of flash-memory chip 12 is over 20 pins. Also, these 20 pins need to be added to controller 10, increasing its pin count.
While chips with 20 or 30 pins are acceptable for many applications, some applications are more sensitive and could benefit by a further reduced pin count. For example, small devices such as flash-memory cards and flash drives are very small and benefit from further reductions in the pin counts, since a reduced pin count can reduce chip package sizes of both flash-memory chip 12 and controller 10, and can reduce the wiring needed and the size of a printed-circuit board (PCB) that flash-memory chip 12 and controller 10 are mounted on. Controller 10 and flash-memory chip 12 can be integrated together as a single integrated circuit (IC) with reduced pin count.
Memory devices are sometimes chained together in a daisy chain. For example, fully-buffered dual-inline memory modules (FB-DIMM) links modules that re-transmit data to downstream modules. Unfortunately, the module that is the farthest away from the host's memory controller has a large latency since data must be retransmitted by all other modules in the daisy chain. This latency problem puts a limit on the number of memory modules that can be chained together.
What is desired is to reduce both latency and the pin count of a flash-memory chip by using a serial interface rather than a parallel interface. A serial interface to a flash-memory chip is desirable. A serial interface using packets to access a flash-memory chip is desirable. It is desired to modify a standardized serial interface for use with a flash-memory chip. A specialized serial interface to a flash-memory chip that is based on a standard serial-bus interface is desirable. It is further desired to reduce latency by arranging the flash-memory chips in a ring topology rather than in a daisy chain. A very high capacity memory system using serial packets sent in a ring is desirable.